Interconnects for connecting masters with slaves so that a CPU for example can access memory and various peripheral devices are known. These interconnects have there own protocols which allow logic within them to deal with and route transaction requests appropriately.
Some systems use memory mapped input/output where the same address bus is used to address both memory and input/output devices and CPU instructions used to address memory are also used to access the devices. In such cases a certain region of memory needs to be reserved for these devices, the code of the CPU instruction or the value of the register used by the instruction then being an indication of the device to be accessed.
In memory mapped systems peripheral devices are mapped to a shared device memory region and the system is designed so that the ordering of transactions sent to these devices is maintained to avoid data coherency problems. Thus, the protocol of the interconnect is designed to ensure that a transaction to this shared memory region that is received after another transaction to the same region does not execute before it.
Satisfying this ordering requirement has been addressed in the prior art, for example in the ARM® AXI bus protocol by marking transaction requests to devices mapped to this address space with a “device” attribute. The AXI protocol then imposes an ordering requirement on these transaction requests requiring them to execute in the order that they are received in. Thus, if the same bus can access two devices mapped to the same address space, the AXI protocol enforces ordering requirements of transaction requests marked with the device attribute on this bus. Alternatively, separate buses may be used to access each of the different devices.
Both solutions to the problem have drawbacks. The use of different buses is expensive in interconnect hardware, while sharing a bus, but using bus logic to enforce the ordering requirements has a drawback where several peripheral devices are mapped to this memory region in that a slow peripheral device that takes a long time to execute a transaction request can hold up many other peripheral devices. This can be a particular problem if one of these peripheral devices needs to perform an action with low latency which is the case for an interrupt controller for example.
It would be desirable to be able to reduce the delays caused by these ordering requirements without unduly increasing the interconnect hardware used.